Implementing machine learning algorithms on programmable chips requires substantial hardware resources and logic blocks, which imposes limitations on their deployment. One effective approach to reduce resource usage is employing approximate computing circuits. Multiplication is typically one of the main targets in approximate computation since it plays a key role in increasing both resource consumption and computational delay. In this paper, approximate 5:2 and 6:2 compressors are proposed for use in a 6-bit multiplier circuit. The proposed design was first simulated using VHDL and then implemented and synthesized in Vivado on a ZedBoard Zynq platform from the Zynq-7000 family. Synthesis results show improvements of 50%, 50%, and 25% in resource utilization, dynamic power consumption, and delay, respectively, compared to the exact design. Error metrics evaluation, including NMED and MRED, demonstrates values comparable to other existing works. For qualitative evaluation, the proposed circuit was applied in a MATLAB-based machine learning model using a feedforward neural network. The results show that the average error increased by only 0.12% and 0.11% in linear regression and edge detection applications, respectively, which are acceptable for such use cases. Since random data were used, a t-test was conducted to analyze the accuracy. The test results indicate that, with a confidence level of 86%, there is no statistically significant difference in accuracy between the approximate and exact models.