نوع مقاله : مقاله پژوهشی
نویسندگان
1 کارشناسی ارشد،دانشگاه جامع امام حسین (ع)، تهران،ایران
2 استادیار،دانشگاه جامع امام حسین (ع)، تهران،ایران
3 کارشناسی ارشد،دانشگاه تربیت مدرس، تهران ، ایران
چکیده
کلیدواژهها
موضوعات
عنوان مقاله [English]
نویسندگان [English]
Current image processing systems have the ability to fast process images with high imaging rates. To reduce calculation time and increase processing speed, algorithms can be implemented on hardware accelerators such as FPGA. The hardware implementation of image processing algorithms should be improved with the aim of increasing the processing speed, reducing the resources consumed and, as a result, reducing the cost of the used processor. In the application of target detection, the optical seeker will be able to detect, recognize and track the target by using image processing algorithms and comparing the current image information of the camera with the information of the desired target image that has already been stored in its processor memory. In this process, SIFT is an algorithm for matching applications, of which the DOG section is one of its subsections. DOG alone covers more than 80% of the execution time of the SIFT algorithm. The reason for this is that many Gaussian filters are multiplied in the input image. The proposed architecture is presented in such a way that only two DSP48s are used for the RTL implementation of each 15x15 Gaussian filter. The advantage of reducing the number of resources related to the cheapness of FPGA has been used. HLS tool has been used to implement the proposed architecture.
In the application of target detection, the optical seeker will be able to detect, recognize and track the target by using image processing algorithms and comparing the current image information of the camera with the information of the desired target image that has already been stored in its processor memory. In this process, SIFT is an algorithm for matching applications, of which the DOG section is one of its subsections. DOG alone covers more than 80% of the execution time of the SIFT algorithm. The reason for this is that many Gaussian filters are multiplied in the input image. The proposed architecture is presented in such a way that only two DSP48s are used for the RTL implementation of each 15x15 Gaussian filter. The advantage of reducing the number of resources related to the cheapness of FPGA has been used. HLS tool has been used to implement the proposed architecture.
کلیدواژهها [English]
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