کاهش تاخیراجرای الگوریتم رمزنگاری پساکوانتوم InvBR-LWE در دستگاه های با منابع محدود

شیری, نادر; عبدلی, حاتم

کاهش تاخیراجرای الگوریتم رمزنگاری پساکوانتوم InvBR-LWE در دستگاه های با منابع محدود

نوع مقاله : مقاله پژوهشی

نویسندگان

¹ کارشناسی ارشد،دانشگاه بوعلی سینا، همدان، ایران

² استادیار،دانشگاه بوعلی سینا، همدان، ایران

چکیده

با گسترش دستگاه‌های اینترنت اشیاء و ظهور کامپیوترهای کوانتومی با چالش جدیدی مواجه هستیم که در زیرساخت‌های اینترنت اشیاء به‌عنوان بخشی از اینترنت و دنیای دیجیتال با حملات مخربی روبرو خواهیم بود. قدرت پردازش کامپیوترهای کوانتومی تا میلیون‌ها برابر کامپیوترهای کلاسیک است و درنتیجه الگوریتم‌های رمزنگاری کلاسیک در معرض شکسته شدن قرار می‌گیرند. همچنین محدودیت منابع در دستگاه‌های IoT و لبه، سختی کار را برای پیاده‌سازی الگوریتم‌های بزرگ و پیچیده دوچندان می‌کند؛ بنابراین نیاز به رویکردهای رمزنگاری سبک‌وزن و درعین‌حال مقاوم در برابر حملات کامپیوترهای کوانتومی و طبیعتاً کامپیوترهای کلاسیک داریم. بر این اساس که کامپیوترهای کوانتومی در مقیاس بزرگ در 15-10 سال آینده در دسترس خواهند بود،NIST فرآیند استانداردسازی رمزنگاری پساکوانتومی را به‌منظور یافتن الگوریتم‌های کلید عمومی جدید و مقاوم در برابر رایانه‌های کوانتومی آغاز کرد. در میان انواع مختلف طرح‌های رمزنگاری مقاوم در برابر کوانتوم، رمزنگاری مبتنی بر مشبکه به‌عنوان یک طرح مقرون‌به‌صرفه و کارا، در حال گسترش است. طرح‌های پیشنهادی مبتنی بر مشبکه براساس مسئله LWE و نوع سبک BR-LWE باهدف پوشش دستگاه‌های با منابع محدود، برای کاهش اندازه کلید و دستیابی به مساحت کمتر، خطاهای باینری را به کار می‌گیرند و درعین‌حال امنیت کافی برای برنامه‌های سبک‌وزن را نیز حفظ می‌کنند. پیاده‌سازی این الگوریتم با چالش‌هایی مانند زمان اجرا، تأخیر و منابع موردنیاز روبه‌رو است. در روش پیشنهادی، یک معماری کارآمد مبتنی بر LFSR برای اجرای موازی و مؤثر ضرب چندجمله‌ای و کاربرد آن در طرح InvBR-LWE ارائه ‌شده است. با تجزیه ضرایب چندجمله‌ای A و B به گروه‌های متعدد و اجرای هم‌زمان در دو مدار موازی، زمان اجرای کل الگوریتم کاهش یافته است. نتایج سنتز بر روی تراشه FPGA نشان می‌دهد که طرح پیشنهادی نسبت به کارهای مشابه، به دلیل کاهش سیکل اجرا، تأخیر کل کمتری دارد و به‌طورکلی معیار ADP روش پیشنهادی تا 35% کاهش‌یافته است. با توجه به نتایج حاصل‌شده، طرح پیشنهادی می‌تواند باعث کاهش تأخیر در کاربردهای سبک‌وزن شود.

کلیدواژه‌ها

20.1001.1.23224347.1404.13.1.10.5

موضوعات

سخت افزار

عنوان مقاله [English]

Reducing delay of InvBR-LWE PQC algorithm in limited-resources devices

نویسندگان [English]

Nader Shiri ¹
Hatam Abdoli ²

¹ Master's degree, Bu-Ali Sina University, Hamedan, Iran

² Assistant Professor, Bu-Ali Sina University, Hamedan, Iran

چکیده [English]

With the expansion of IoT devices and the emergence of quantum computers, new security challenges have arisen. One significant concern is the vulnerability of IoT infrastructure to malicious attacks, given its integral role in the Internet and digital ecosystems. Quantum computers possess processing power millions of times greater than that of classical computers, rendering traditional cryptographic algorithms susceptible to decryption. Furthermore, resource constraints in IoT and edge devices exacerbate the difficulty of implementing large and complex cryptographic algorithms. Consequently, there is a pressing need for lightweight cryptographic approaches that offer resistance to both quantum and classical attacks. Given that large-scale quantum computers are anticipated to become available within the next 10–15 years, the NIST has initiated the post-quantum cryptography standardization process to identify new public-key algorithms that can withstand quantum attacks. Among the various quantum-resistant cryptographic schemes, lattice-based cryptography has emerged as a promising, cost-effective, and efficient solution. Specifically, lattice-based schemes derived from LWE problem and BR-LWE model are designed to address the constraints of resource-limited devices. These schemes leverage binary errors to minimize key sizes and reduce hardware requirements while maintaining sufficient security for lightweight applications. However, implementing such algorithms presents challenges, including execution time, latency, and resource demands. In this study, an efficient LFSR-based architecture is proposed to facilitate parallel and efficient polynomial multiplication, which is critical for InvBR-LWE scheme. By decomposing polynomial coefficients and into multiple groups and executing them simultaneously in two parallel circuits, the overall execution time of the algorithm is significantly reduced. Synthesis results on an FPGA chip demonstrate that the proposed scheme achieves lower total latency than existing approaches due to a reduced execution cycle. Overall, the ADP criterion of the proposed method is improved by 35%. These findings indicate that the proposed scheme effectively reduces latency in lightweight cryptographic applications.

کلیدواژه‌ها [English]

Post-quantum cryptography
InvBR-LWE
IoT Security
Lattice-Based Algorithms
polynomial multiplication
hardware implementation

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