Reducing delay of InvBR-LWE PQC algorithm in limited-resources devices

Document Type : Original Article

Authors

1 Master's degree, Bu-Ali Sina University, Hamedan, Iran

2 Assistant Professor, Bu-Ali Sina University, Hamedan, Iran

Abstract

With the expansion of IoT devices and the emergence of quantum computers, new security challenges have arisen. One significant concern is the vulnerability of IoT infrastructure to malicious attacks, given its integral role in the Internet and digital ecosystems. Quantum computers possess processing power millions of times greater than that of classical computers, rendering traditional cryptographic algorithms susceptible to decryption. Furthermore, resource constraints in IoT and edge devices exacerbate the difficulty of implementing large and complex cryptographic algorithms. Consequently, there is a pressing need for lightweight cryptographic approaches that offer resistance to both quantum and classical attacks. Given that large-scale quantum computers are anticipated to become available within the next 10–15 years, the NIST has initiated the post-quantum cryptography standardization process to identify new public-key algorithms that can withstand quantum attacks. Among the various quantum-resistant cryptographic schemes, lattice-based cryptography has emerged as a promising, cost-effective, and efficient solution. Specifically, lattice-based schemes derived from LWE problem and BR-LWE model are designed to address the constraints of resource-limited devices. These schemes leverage binary errors to minimize key sizes and reduce hardware requirements while maintaining sufficient security for lightweight applications. However, implementing such algorithms presents challenges, including execution time, latency, and resource demands. In this study, an efficient LFSR-based architecture is proposed to facilitate parallel and efficient polynomial multiplication, which is critical for InvBR-LWE scheme. By decomposing polynomial coefficients and into multiple groups and executing them simultaneously in two parallel circuits, the overall execution time of the algorithm is significantly reduced. Synthesis results on an FPGA chip demonstrate that the proposed scheme achieves lower total latency than existing approaches due to a reduced execution cycle. Overall, the ADP criterion of the proposed method is improved by 35%. These findings indicate that the proposed scheme effectively reduces latency in lightweight cryptographic applications.

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References

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Electronic and Cyber Defense
Volume 13, Issue 1 - Serial Number 49
Spring
April 2025
Pages 131-143

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History

  • Receive Date: 08 December 2024
  • Revise Date: 19 February 2025
  • Accept Date: 13 March 2025
  • Publish Date: 21 April 2025

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