Introducing a new timing attack on the ARM processor and its practical implementation on the Raspberrypi3 board

Document Type : Original Article

Authors

Shahid beheshti of university

Abstract

An important category of the side-channel attacks takes advantage of the fact that cache leads to temporal changes in the execution of encryption algorithms and thus information leakage. Although side-channel attacks based on high cache memory are among the most widely used side-channel attacks, they have been less studied than other side-channel attacks. Accordingly, extensive research has been conducted by the cryptographic community in the area of ​​side-channel attacks based on cache memory.The focus of research has mainly been on the security of encryption algorithms implemented by Intel and Pentium processors, which due to the different cache structure of different processors, cannot be extended to other commonly used processors such as ARM. In response to this challenge, new research is focusing on cache-based side-channel attacks on various mobile processors and other applications including ARM processors. The different cache structure and lack of support for some of the commands needed to execute cache attacks have made it difficult to execute these attacks on ARM processors. In this paper, we first investigate the cache-timing attack using a collision event on one of the ARM processors. In this attack, the attacker only needs to measure the timing of the encryption, and unlike the access-driven attacks, the attacker does not need access to the victim's cache. We also implemented the attack using an industrial automation board called Raspberrypi3, which runs the router operating system, the results of which show the accuracy of the attack.

Keywords

References

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History

  • Receive Date: 10 September 2018
  • Revise Date: 14 September 2019
  • Accept Date: 19 November 2019
  • Publish Date: 21 May 2020

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