Designing Systolic Array for SL0 Algorithm Implementation

Document Type : Original Article

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Abstract

Systolic architecture is one of most important parallel processing architectures.In the systolic array, ALU units are arranged as an array. This array acts synchronously and executes the recursive equations in parallel by applying the proper input. In this paper, the systolic array for the SL0 is designed and simulated. Simulation results showed that the implementation of this algorithm with a single processor, assuming 4 clocks for executing each recursive equation, requires 4N ^ 3 + 9.7N ^ 2 + 3.2N + 18 clocks, while doing it with a systolic array requires 48n + 32 clocks due to parallel computing and pipelines.

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References

 
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History

  • Receive Date: 24 February 2019
  • Revise Date: 04 May 2019
  • Accept Date: 18 June 2019
  • Publish Date: 20 February 2020

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