Design and Production of Hardware Authentication Code Using Physically Unclonable Functions and a Random Number Generator on FPGA

Document Type : Original Article

Authors

1 عضو هیات علمی

2 کارشناس ارشد

3 -

Abstract

 One of the most challenging issues in the field of hardware security is to protect the hardware from reverse engineering, counterfeiting and cloning. Using Physically Unclonable Functions (PUFs) is among the most efficient ways to improve security against these kinds of threats. In this work, we used a multiplexer-based or the so-called arbiter PUF to improve resilience of FPGAs from Xilinx family against these types of vulnerabilities. At first, a 32-bit random code was generated as the initial seed for a linear feedback shift register (LFSR). Then, a 64-bit unique authentication code was generated by XORing the outputs of the shift register and outputs of a ring oscillator-based random number generator and passing out the result from the Von Neumann corrector. The scheme is implemented in such a way that the generated code is robust against reverse engineering or modeling, and therefore is unrecoverable. The implementation results, on Side-Channel Attack User Reference Architecture (SAKURA G-II) which includes XC6SLX75 demonstrated that the design utilizes almost 15% of FPGA resources to generate a 64-bit unique authentication code.

Keywords

References

[1]     R. Maes, “Physically Unclonable Functions: Constructions, Properties and Applications,” Ph. D. thesis, Dissertation, University of KU Leuven, 2012.##
[2]     H. Handschuh, S. Geert-Jan, and P. Tuyls, “Hardware Intrinsic Security from Physically Unclonable Functions,” Parts of Towards Hardware-Intrinsic Security, Springer Berlin Heidelberg, pp. 39-53, 2010.##
[3]     M. Platonov, “SRAM-Based Physical Unclonable Function on an Atmel ATmega Microcontroller,” Master’s thesis, Czech Technical University in Prague, Faculty of Information Technology, 2013.##
[4]     V. Van der Leest, G.-J. Schrijen, H. Handschuh, and P. Tuyls, “Hardware Intrinsic Security from D Flip-Flops,” In ACM Workshop on Scalable Trusted Computing—STC 2010, New York: ACM, pp. 53–62, 2010.##
[5]     J.-L. Zhang, “A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs,” Journal of Computer Science and Technology, vol. 29, no. 4, pp. 664–678, July 2014. DOI 10.1007/s11390-014-1458-1.##
[6]     C.-H. Chang, Y. Zheng, and L. Zhang, “A Retrospective and a Look Forward: Fifteen Years Feature Abstract of Physical Unclonable Function Advancement,” IEEE Circuits and Systems Magazine, vol. 17, Issue 3, pp. 32-62, 2017.##
[7]     J. Guajardo, S. S. Kumar, G. Schrijen, and P. Tuyls, “FPGA Intrinsic PUFs and Their Use for IP Protection,” CHES 2007, LNCS 4727, pp. 63–80, 2007.##
[8]     N. Beckmann and M. Potkonjak, “Hardware-Based      Public-Key Cryptography with Public Physically Unclonable Functions,” In Lecture notes in computer science (LNCS): vol. 5806, International workshop on information     hiding—IH 2009, Berlin: Springer, pp. 206–220, 2009.##
[9]     L. Bolotny and G. Robins, “Physically Unclonable  Function-Based Security and Privacy in RFID Systems,” In IEEE international conference on pervasive computing and communications—PERCOM 2007, New York: IEEE, pp. 211–220, 2007.##
[10]  F. Armknecht, R. Maes, A.-R. Sadeghi, B. Sunar, and P. Tuyls, “Memory Leakage Resilient Encryption Based on Physically Unclonable Functions,” In Lecture Notes In Computer Science (LNCS): vol. 5912, Advances in Cryptology—ASIACRYPT 2009, Berlin: Springer, pp.  685–702, 2009.##
[11]  L. Lin, S. Srivathsa, D. K. Krishnappa, P. Shabadi, and W. Burleson, “Design and Validation of Arbiter-Based PUFs for Sub-45-nm Low-Power Security Aapplications. IEEE Trans. Inf. Forensics and Security, vol. 7, no. 4, pp. 1394-1403, 2012.##
[12]  M. Z. Shahrak, “Secure and Lightweight Hardware Authentication Using Isolated Physical Unclonable Function,” MS Thesis, University of Nebraska-Lincoln, 2016.##
[13]  J. Delvaux and I. Verbauwhede, “Side Channel Modeling Attacks on 65nm Arbiter PUFs Exploiting CMOS Device Noise,” In Proc. IEEE Int. Symposium on Hardware-Oriented Security and Trust, pp. 137-142, 2013.##
[14]  M. Usmani, “Applications of Physical Unclonable Functions on ASICS and FPGAs,” MS Thesis, University of Massachusetts Amherst, 2018.##
[15]  W. Stallings, “Cryptography and Network Security,” 5th Ed., Pearson, 2014.##
[16]  S. Katzenbeisser, U. Kocaba, V. Rozic, A. R. Sadeghi, and I. Verbauwhede, and C. Wachsmann, “PUFs: Myth, Fact or Busted? A Security Evaluation of Physically Unclonable Functions (PUFs) Cast In Silicon,” In Proceedings of the 14th Int. Conference on Cryptographic Hardware and Embedded Systems (Berlin, Heidelberg, 2012), CHES'12, Springer-Verlag, pp. 283-301, 2012.##
[17]  J. Guajardo, S. S. Kumar, G. J. Schrijen, and P. Tuyls, “FPGA Intrinsic PUFs and Their Use for IP protection,” In Lecture Notes In Computer Science (LNCS), vol. 4727, Workshop on Cryptographic Hardware and Embedded Systems—CHES 2007,  Berlin: Springer, pp. 63–80, 2007.##
[18]  S. Kumar, J. Guajardo, R. Maes, G.-J. Schrijen, and P. Tuyls, “Extended abstract: The Butterfly PUF Protecting IP on Every FPGA,” In IEEE International Symposium on Hardware Oriented Security and Trust—HOST 2008, New York: IEEE, pp. 67–70, 2008.##
[19]  T. Machida, D. Yamamoto, M. Iwamoto, and K. Sakiyama, “A New Mode of Operation for Arbiter PUF to Improve Uniqueness on FPGA. In 2014 Federated Conference on Computer Science and Information Systems, pp. 871-878, Sept. 2014.##
[20]  R. Maes, A. Van Herrewege, and I. Verbauwhede, “PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator,” In Lecture notes in computer science (LNCS): vol. 7428, Workshop on Cryptographic Hardware and Embedded Systems—CHES 2012, Berlin: Springer, 2012.##
[21]  G. E. Suh and S. Devadas, “Physical Unclonable Functions for Device Authentication and Secret Key Generation,” In Proc. The 44th ACM/IEEE Design Automation Conference, Jun. 2007, pp. 9-14, 2007.##
[22]  A. Cherkaoui, V. Fischer, A. Aubert, and L. Fesquet, “Comparison of Self-Timed Ring and Inverter Ring Oscillators as Entropy Sources in FPGAs,” In Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 1325-1330, 2012.##
[23]  S. Gujja, “Temperature Variation Effects on Asynchronous PUF Design Using FPGAs,” PhD Thesis, University of Toledo, http://utdr-toledo.edu/theses-dissersions, 2014.##
[24]  K. B. Frikken, M. Blanton, and M. J. Atallah, “Robust Authentication Using Physically Unclonable Functions,  P. Samarati et al. (Eds.): ISC 2009, LNCS 5735, pp. 262–277, 2009.##
[25]  M. Barbareschi, et al., “A PUF-based Hardware Mutual Authentication Protocol,” J. Parrallel and Distributed Computing, 2018. https://doi.org/10.1016/j.jpdc.2018.04.007.##
[26]  T. E. Tkacik, “A Hardware Random Number Generator,” Proc. of CHES 2002, pp. 450- 453, 2002.##
[27]  M. Epstein, L. K. Hars, H. Z. Raymond, “Design and Implementation of a True Random Number Generator Based on Digital Circuit Artifacts,” CHES 2003, pp. 152-165, 2003.##
[28]  M. Dichtl and D. J. Golic, “High-Speed True Random Number Generation with Logic Gates Only,” CHES 2007, 2007. https://iacr.org/archive/ches2007/47270045/47270045.pdf.##
[29]  W. P. Kohlbrenner, “The Design and Analysis of a True Random Number Generator in a Field Programmable Gate Array,” Proc. of International Symposium on FPGAs, 2004.##
[30]  B. Sunar, W. J., Martin, and D. R. Stinson, “A Provably Secure True Random Number Generator with Built-in Tolerance to Active Attacks,” IEEE Transactions on Computers, vol. 56, Issue 1, pp. 109-119, 2007.##
[31]  A. Rukhin, “A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications,” US National Institute of Standards and Technology (NIST), 2001.##
[32]  https://sourceforge.net/projects/randomanalysis/##

Files

History

  • Receive Date: 01 February 2019
  • Revise Date: 26 April 2019
  • Accept Date: 18 June 2019
  • Publish Date: 20 February 2020

Share

How to cite

Statistics