Optimal Design of Low-power High-resolution Unity-STF S-MASH Sigma Delta Modulator for Telecommunication Applications

Document Type : Original Article

Authors

1 Azad university

2 sharif university

Abstract

Given the importance of signal processing in the digital domain, improving the hardware performance of the transmitter-receiver communication systems, especially in the military section, depends on the proper design of the converters that perform the signal conversion from analogue to digital and vice versa. This paper proposes a novel method to improve the modulator speed and resolution in the Sturdy Multi-Stage Noise-Shaping (S-MASH) sigma delta analogue to digital convertor (ADC). Since any stage in the         modulator loop of the architecture has unity signal transfer function (Unity-STF), the modulator would be very robust to circuit non-idealities such as finite op-amp gain and coefficient mismatching. Furthermore, the signal processing timing issue in the critical paths of the proposed architecture has been relaxed due to shifting the delay of each stage of the modulator loop filter to its own feedback path. On the other hand, the proposed Unity-STF S-MASH architecture needs fewer active blocks for implementation which makes it suitable for low power, high operation speed applications i.e. communication systems. The simulation    results show the effectiveness of the proposed architecture. Since the information processing is an important category in the field of management and crisis prevention, the design would be applicable in the electronic hardware equipment related to this area.
 

Keywords

References

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History

  • Receive Date: 29 March 2018
  • Accept Date: 13 October 2018
  • Publish Date: 22 June 2019

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