Efficient design and implementation of LMS adaptive digital filter on FPGA chip

Author

Assistant Professor, Islamic Azad University, Islamshahr branch, Islamshahr, Iran

Abstract

Adaptive filters are an important part of many digital signal processing systems and are used in various applications such as echo removal, noise removal, radar systems, sonar, etc. The hardware implementation of signal processing systems has advantages such as higher speed and efficiency, the possibility of integration and parallel processing capability compared to its software implementation


Nowadays, FPGA chips are mainly used for the hardware implementation of digital systems due to having features such as parallel information processing, architectural flexibility... Efficient implementation of adaptive filters on FPGA chips is important and challenging at the same time because these filters, unlike non-adaptive filters, require repetition of calculations to reach optimal weights.




In this article, an efficient hardware implementation of the least mean square algorithm known as LMS is presented, which, compared to the implementation reported in the relevant literature, has a higher working frequency and less occupied area on the chip. The validity of the obtained results has been verified by comparing the implementation results with the results obtained from the simulation of an LMS adaptive filter for noise removal.
Since the permanent collection and processing of information and significant environmental signs is one of the important elements in the cycle of crisis management and prevention, such as warning systems and passive defense, therefore, the presented design can It should be used in the tools and hardware tools related to this category.
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Keywords

References

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History

  • Receive Date: 11 February 2016
  • Revise Date: 16 October 2024
  • Accept Date: 19 September 2018
  • Publish Date: 14 March 2017

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